The collected works of ivelegacy - Page 4

foetz wrote: also going from extreme to impact requires a new backplane and a new psu so the switch is not cheap at all.

• 1993, January, Indigo 2 systems introduced with R4400 CPU and Extreme graphics
• 1993, 1st half (approx.)Challenge M, L and XL systems with R4400 processor introduced
• 1993, July, XZ and XL graphics announced
• 1995, Indigo 2 systems with Impact graphic s introduced
• 1995, July, R4400 with 250 MHz announced
• 1995, August, Webforce systems announced for September
• 1996, January, R10000 processors for Indigo 2 Impact systems announced
• 1997, September, End of Production (non-Impact)
• 1998, June, End of Production (Impact)
• 2006, December, EOS, End of Service

• the RTC-memory
• the audio board (1)

The SGI O2 had an Imaging and Compression Engine (ICE) application-specific integrated circuit (ASIC) for processing streaming media and still images. ICE operates at 66 MHz and contains a R3000-derived microprocessor serving as the scalar unit to which a 128-bit SIMD unit is attached using the MIPS coprocessor interface. ICE operates on eight 16-bit or sixteen 8-bit integers, but still provides a significant amount of computational power which enables the O2 to do video decoding and audio tasks that would require a much faster CPU if done without SIMD instructions. ICE only works with the IRIX operating system, as this is the only system that has drivers capable of taking advantage of this device.

The Unified Memory Architecture means that the O2 uses main memory for graphics textures, making texturing polygons and other graphics elements trivial. Instead of transferring textures over a bus to the graphics subsystem, the O2 passes a pointer to the texture in main memory which is then accessed by the graphics hardware. This makes using large textures easy, and even makes using streaming video as a texture possible.

Since the CPU performs many of geometry calculations, using a faster CPU will increase the speed of a geometry-limited application. The O2's graphics is known to have slower rasterization speed than the Indigo2's Maximum IMPACT graphics boards, though the Maximum IMPACT graphics is limited to 4 MB of texture memory, which can result in thrashing, whereas the O2 is limited only by available memory.

While CPU frequencies of 180 to 400 MHz seem low today, when the O2 was released in 1996, these speeds were on par with or above the current offerings for the x86 family of computers (cf. Intel's Pentium and AMD's K5). Further, the above listed features made it an excellent graphics workstation which was the market it was targeted at. It was however, even with the speed upgrades it consequently received, not able to keep up with the mainstream PC market and cheaper x86 based computers started to outperform it by the end of its lifetime.

TeamBlackFox wrote: but Pascal itself isn't on the CDs of course

mapesdhs wrote: You've linked to my mirror site, I'm the latter guy.

mapesdhs wrote: By contrast, the modded R12K/300 is IMO a far better option

• Xbow v1.4 (it's a must!)
• R10K, R12K CPU
• Impact/SR (1), or odissey gfx V6, V8 (i prefer SSE)

The graphics options available for the SGI Indigo² can be divided in two groups: the "pre-IMPACT" and the "MGRAS IMPACT" boards.

"Pre-IMPACT" options consisted of the following options: SGI XL24, SGI XZ, SGI Elan and SGI Extreme). These options are based on the same "Express Graphics" architecture from the original SGI Indigo, but feature improved performance.

The "MGRAS IMPACT" boards include: Solid IMPACT, High IMPACT, High IMPACT AA, and the Maximum IMPACT, and are also known as the IMPACT graphics family. These newer boards have a different architecture than the earlier designs. Physically, they appear to be similar to the older graphics options - the low-end Solid IMPACT board takes up a single GIO-64 slot, the mid-range High IMPACT takes up two GIO-64 slots, and the high end Maximum IMPACT takes occupies three. The High IMPACT and Solid IMPACT boards provides the same performance for non-textured tasks, while the Maximum IMPACT provides double the performance. The High IMPACT AA option has the geometry performance of a Maximum IMPACT, but is otherwise the same as the High IMPACT including the pixel fill performance.

The IMPACT graphics was the first desktop graphics system from SGI to offer texture mapping acceleration, though only the High IMPACT and Maximum IMPACT had this capability, and came with 1 MB of texture memory as standard. The Solid IMPACT card is named "Solid" due to its applications for solid (non-textured) modeling. When expanded by adding a TRAM (Texture RAM) module to the board, the amount of texture memory can be increased to 4 MB. Maximum IMPACT graphics require two of these modules due its two pixel units, although this does not upgrade them to 8 MB, with the two modules merely working in parallel to render twice as fast. At the time of its release, Maximum IMPACT graphics was the world's fastest available top-end desktop visualization solution. A Maximum IMPACT with 4 MB of texture memory and the correct graphics settings can play id Software's Quake 1, 2 or 3 with acceptable frame rates.

A Maximum IMPACT with 4 MB of texture memory and the correct graphics settings can play id Software's Quake 1, 2 or 3 with acceptable frame rates.

vishnu wrote: For the mathmatically inclined, the linear algebra pack is available on IRIX:

Ubiquitous techpubs link.

And

linear algebra pack homepage

NEW Unix Systems for Modern Architectures: Symmetric Multiprocessing and Caching
Detailed info

Synopsis
Any UNIX programmer using the latest workstations or super minicomputers from vendors such as Sun, Silicon Graphics (SGI), ATandT, Amdahl, IBM, Apple, Compaq, Mentor Graphics, and Thinking Machines needs this book to optimize his/her job performance. This book teaches how these architectures operate using clear, comprehensible examples to explain the concepts, and provides a good reference for people already familiar with the basic concepts.

READ THE SENSATIONAL BLOCKBUSTER THAT STARTED IT ALL! Take it from the top in # 1 New York Times bestselling author Sue Grafton's knockout thriller that introduced detective Kinsey Millhone-and a hot new attitude-to crime fiction... A IS FOR AVENGER A tough-talking former cop, private investigator Kinsey Millhone has set up a modest detective agency in a quiet corner of Santa Teresa, California. A twice-divorced loner with few personal possessions and fewer personal attachments, she's got a soft spot for underdogs and lost causes. A IS FOR ACCUSED That's why she draws desperate clients like Nikki Fife. Eight years ago, she was convicted of killing her philandering husband. Now she's out on parole and needs Kinsey's help to find the real killer. But after all this time, clearing Nikki's bad name won't be easy. A IS FOR ALIBI If there's one thing that makes Kinsey Millhone feel alive, it's playing on the edge. When her investigation turns up a second corpse, more suspects, and a new reason to kill, Kinsey discovers that the edge is closer-and sharper-than she imagined.

This book represents a significant new milestone in UNIX kernel internals books. Symmetric multiprocessing and cache memory systems are important cost-effective technologies for improving performance in today's state-of-the-art systems. Written for the UNIX kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches and symmetric multiprocessors, how they work together, and the issues operating systems must address in order to run on the machines that incorporate them. After a review of UNIX kernel internals, Curt Schimmel launches into a detailed description of cache memory systems, including several kinds of virtual and physical caches, as well as a chapter on efficient cache management. For each type of cache, the book covers the impact on the software and the operating system changes necessary for these systems. The next section details the operation of the tightly-coupled, shared memory, symmetric multiprocessor. It examines the problems these multiprocessors present to the operating system, such as race conditions, deadlocks, and the ordering of memory operations, and looks at how the UNIX kernel can be adapted to run on such systems. Finally, the book looks at the interaction between cache memory systems and multiprocessors and the new problems that this interaction presents to the kernel. Techniques for solving these problems are then explained. Numerous examples representing CISC and RISC processors, such as the Intel 80486 and Pentium, the Motorola 68040 and 88000, as well as theMIPS and SPARC processors, illustrate the concepts presented. To reinforce the concepts, each chapter contains a set of exercises with answers to selected exercises included in the back."This book UNIX Systems for Modern Architectures for the systems programmer covers almost everything you wanted to know about caches, multiprocessor systems, and cached multiprocessor systems, especially as related to UNIX."-Unix Review 0201633388B04062001

Written for the UNIX & amp; kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches and tightly-coupled, shared memory symmetric multiprocessors, how they work together, and the issues operating systems must address in order to run on the machines the incorporate them. After a detailed description of the operating system changes required by various cache architectures, Schimmel covers the kernel modifications needed to address the issues presented by symmetric multiprocessors, such as race conditions, deadlocks, and the correct ordering of memory operations. Illustrating the concepts presented are numerous examples using current CISC and RISC processors, including MIPS and SPARC.

Written for the UNIX & kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches and tightly-coupled, shared memory symmetric multiprocessors, how they work together, and the issues operating systems must address in order to run on the machines the incorporate them. After a detailed description of the operating system changes required by various cache architectures, Schimmel covers the kernel modifications needed to address the issues presented by symmetric multiprocessors, such as race conditions, deadlocks, and the correct ordering of memory operations. illustrating the concepts presented are numerous examples using current CISC and RISC processors, including MIPS and SPARC.

Written for the UNIX & kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches and tightly-coupled, shared memory symmetric multiprocessors, how they work together, and the issues operating systems must address in order to run on the machines the incorporate them. After a detailed description of the operating system changes required by various cache architectures, Schimmel covers the kernel modifications needed to address the issues presented by symmetric multiprocessors, such as race conditions, deadlocks, and the correct ordering of memory operations. illustrating the concepts presented are numerous examples using current CISC and RISC processors, including MIPS and SPARC.

Written for the UNIX && kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches and tightly-coupled, shared memory symmetric multiprocessors, how they work together, and the issues operating systems must address in order to run on the machines the incorporate them. After a detailed description of the operating system changes required by various cache architectures, Schimmel covers the kernel modifications needed to address the issues presented by symmetric multiprocessors, such as race conditions, deadlocks, and the correct ordering of memory operations. Illustrating the concepts presented are numerous examples using current CISC and RISC processors, including MIPS and SPARC.

Written for the UNIX kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches and tightly-coupled, shared memory symmetric multiprocessors, how they work together, and the issues operating systems must address in order to run on the machines the incorporate them. After a detailed description of the operating system changes required by various cache architectures, Schimmel covers the kernel modifications needed to address the issues presented by symmetric multiprocessors, such as race conditions, deadlocks, and the correct ordering of memory operations. Illustrating the concepts presented are numerous examples using current CISC and RISC processors, including MIPS and SPARC.

Product Identifiers
ISBN-10 0201633388
ISBN-13 9780201633382

Key Details
Author Curt Schimmel
Number Of Pages 432 pages
Series Addison-Wesley Professional Computing Ser.
Format Paperback
Publication Date 1994-06-30
Language English
Publisher Addison Wesley Professional

Additional Details
Copyright Date 1994

Target Audience
Group Scholarly & Professional

Classification Method
LCCN 94-014555
LC Classification Number QA76.76.O63S3756
Dewey Decimal 005.4/2
Dewey Edition 20

Table Of Content

• Preface. Notational Conventions. Introduction.
• 1. Review of UNIX Kernel Internals. Introduction. Processes, Programs, and Threads. The Process Address Space. Context Switch. Memory and Process Management System Calls. Summary. Exercises. Further Reading. I. CACHE MEMORY SYSTEMS. @CHAPTER
• 2. Introduction to Cache Memory Systems. Memory Hierarchies. Cache Fundamentals. Direct Mapped Caches. Two-Way Set Associative Caches. n-Way Set Associative Caches. Fully Associative Caches. Summary of n-Way Set Associative Caches. Cache Flushing. Uncached Operation. Separate Instruction and Data Caches. Cache Performance. How Cache Architectures Differ. Exercises. Further Reading.
• 3. Virtual Caches. Virtual Cache Operation. Problems with Virtual Caches. Managing a Virtual Cache. Summary. Exercises. Further Reading.
• 4. Virtual Caches with Keys. The Operation of a Virtual Cache with Keys. Managing a Virtual Cache with Keys. Virtual Cache Usage in MMUs. Summary. Exercises. Further Reading.
• 5. Virtual Caches with Physical Address Tags. The Organization of a Virtual Cache with Physical Tags. Managing a Virtual Cache with Physical Tags. Summary. Exercises. Further Reading.
• 6. Physical Caches. The Organization of a Physical Cache. Managing a Physical Cache. Multilevel Caches. Primary Virtual Cache with Secondary Physical Cache. Summary. Exercises. Further Reading.
• 7. Efficient Cache Management Techniques. Introduction. Address Space Layout. Cache Size Bounded FlushingDelayed Cache Invalidations. Cache-Aligning Data Structures. Summary. Exercises. Further Reading. II. MULTIPROCESSOR SYSTEMS.
• 8. Introduction to Multiprocessor Systems. Introduction. The Tightly Coupled, Shared Memory, Symmetric. Multiprocessor. The MP Memory Model. Mutual Exclusion. Review of Mutual Exclusion on Uniprocessor. UNIX Systems. Problems Using UP Mutual Exclusion Policies on MPs. Summary. Exercises. Further Reading.
• 9. Master-Slave Kernels. Introduction. Spin Locks. Deadlocks. Master-Slave Kernel Implementation. Performance Considerations. Summary. Exercises. Further Reading.
• 10. Spin-Locked Kernels. Introduction. Giant Locking. Multithreading Cases Requiring No Locks. Coarse-Grained Locking. Fine-Grained Locking. Effects of Sleep and Wakeup on Multiprocessors. Summary. Exercises. Further Reading.
• 11. Semaphored Kernels. Introduction. Deadlocks. Implementing Semaphores. Coarse-Grained Semaphore Implementations. Multithreading with Semaphores. Performance Considerations. Summary. Exercises. Further Reading.
• 12. Other MP Primitives. Introduction. Monitor. Eventcounts and Sequencers.

jpstewart wrote: Since the hint that foetz gave you earlier in the thread didn't seem to help, I'll be more blunt: you'll need the "Development Foundation" and "Development Libraries" CDs from the full Irix install set.

foetz wrote: that's one of the source files of your compiler, not irix.

foetz wrote: as for the missing symbols, i don't know what came with your compiler but in case there were some libs just make sure to link them

foetz wrote: and what's wrong with that?

jan-jaap wrote: GNU Pascal, like Fortran, Ada and a couple of other languages is (was?) an add-on to GCC

jan-jaap wrote: Now, normally copying binary code around between different compiler versions is considered evil. YMMV. You may also wonder how much of your time you want to invest in a compiler where the last version is based on GCC 2.something, incomplete and nobody bothered to fix that in 13 years

jan-jaap wrote: That's why there are two versions on the download page: one with the GCC version included, and one without.

jan-jaap wrote: I copied them from a GCC 3.4.6 into the correct directory for GPC (where libcgcc.a is) and then it works. At least, it works enough to compile a working hello world program.

vishnu wrote: Concur. Fuels can be faster but still lose to dual CPU Octanes

TeamBlackFox wrote: Not if its a 900MHz Fuel :p.

jan-jaap wrote: Fuel will take a SATA card (disks limited to 2TB)

jan-jaap wrote: U160 SCSI is possible in the Octane, but only external (and it requires a PCI shoebox / shoehorn)

Trippynet wrote: Although saying that, the 800MHz and particularly 900MHz Fuels also hold their value well too