Interesting 29K and
Mill
(by "Gandalf" professor, aka Ivan Godard )
I have to study their ISA as they are completely unknown to me
Arise V1 and V2 come with two operating modes: { kernel, user }
in user mode, each task owns its private 32 registers, { r0..r31 }
in kernel mode, the kernel own its private 32 registers, { r0..r31 }, but can also access everything
so, from the kernel mode point of view, all the task's registers are accessible through load/store
as they appear "memory mapped" within the the first 32Kbyte of ram { 0x0000..0x7ffff }
task000 { r0..r31 } <---- mapped at 0x0000 in kernel mode, reserved to kernel, more specifically for interrupts/exceptions
task001 { r0..r31 } <---- mapped at 0x0200 in kernel mode, the user task can access each of them as common registers
task002 { r0..r31 }
task003 { r0..r31 }
..
task255 { r0..r31 }
in user mode, if a task attempts to access the { 0x0000..0x7ffff } range, a trap will issued forcing the kernel mode
with the CAUSE register set with { privilege violation, task attempted to access the registers area }
the ISA in Arise doesn't limit, the upper limit (how many windows registers you can have) is under the the process of putting a decision or plan into effect, more specifically you can virtually implement more than 256 windows (it requires 32Kbyte of BRAM inside the FPGA, and the equivalent silicon in HDL), if you have the resources, in my case, my fpga is limited to 48Kbyte of usable BRAM, bigger fpga add more BRAM
255 usable tasks are more than what I need, and everything else will be implemented with an external NVRAM (2Mbyte), plus a DRAM (8Mbyte), so, about the first prototype (I will use the Papilio/Pro board, Xilinx Spartan6e + expansion), I am feeling fine
What do you think about this feature of Arise
?
) or confused (I have definitely already heard that name and it's already used to describe other things, my disappoint
)
