Everything Else

uunix wrote:

skywriter wrote: Binge-watching BSG reboot (who in their right mind could watch the 1st one?) for the 4th time. I discovered this gem late in life.

What? What? New Battle Star? Where? How? When? How do I get this?

What? You're kidding. It's the 2004-2009 one.

@vishnu I bought the DVD version too. But now that it's back up on HULU - I watch it there; more convenient.

skywriter wrote:

uunix wrote:

skywriter wrote: Binge-watching BSG reboot (who in their right mind could watch the 1st one?) for the 4th time. I discovered this gem late in life.

What? What? New Battle Star? Where? How? When? How do I get this?

What? You're kidding. It's the 2004-2009 one.

@vishnu I bought the DVD version too. But now that it's back up on HULU - I watch it there; more convenient.

Oh.. I thought it was some new one.. ah well, there is always the next V

Well, there was Caprica, but I don't think anybody watched it. I thought the the girl was pretty cute though...

i watched it and it was just as pointless as bsg
actually i'm not sure why i watched it after bsg wasn't my thing at all. guess i'm an optimist

In order to get BSG I think you have to watch every episode, in order. I can see where if you came in in the middle and skipped episodes it would be hard to get the point. They were covering topics in their society, the equivalent of which in our society no one's willing to go near, in terms of popular entertainment. I don't ordinarily agree with the New York Times about anything, but what their reviewer said I think was true, it was the best show on tv at the time...

I watched Caprica; not a great show - didn't seem to go anywhere worth following. You definitely had to watch every episode - in order - of BSG; It's not like it was Gilligans Island after all.

vishnu wrote: Well, there was Caprica, but I don't think anybody watched it. I thought the the girl was pretty cute though...

Alessandra Torresani
Now.. still as hot

The first version was done to pass a computer science examination, the second version attempts to be an hobby fun, the above is the simulator I wrote in order to reinvent the wheel, as I have designed a completely new ISA (it's RISC-like, but with interlocking stages), which comes with its debug processor over its TAP, it stands for test access point, which is not jtag, and talks on the serial console with its own protocol

Interrupting cow!!! architecture!

skywriter wrote: Interrupting cow!!! architecture!

a roundup of cattle on a ranch for branding, counting, one of these was called "arise"
like the cow architecture which switch makes the computer science like a rodeo
welcome into the new century where you can still exhibit us your cowboy-on-the-console
skill at riding broncos, roping calves, wrestling steers

do you mean something like that ?

the TAP behind the cow processor called Arise

I believe I'd better choose a more hipster name for the test access point of my debug processor inside the Arise processor, otherwise those guys in IEEE 1149.1 standard, which was created by the JTAG subcommittee, will ask me to pay the Copyright, and people will be not impressed (I apparently have already heard that name, uuuu ) or confused (I have definitely already heard that name and it's already used to describe other things, my disappoint )

feel free to suggest me a funnier (1) one for Arise v3


(1) constrains: causing laughter or amusement, humorous, witty, comic, comical, droll, facetious, jocular, jockey, hilarious, hysterical, riotous, uproarious, entertaining, diverting, sparkling, scintillating, silly, farcical, slapstick, side-splitting, rib-tickling, laugh-a-minute, wacky, zany, off the wall, a scream, rich, priceless, difficult to explain and understand, strange

ivelegacy wrote: (1) constrains: causing laughter or amusement, humorous, witty, comic, comical, droll, facetious, jocular, jockey, hilarious, hysterical, riotous, uproarious, entertaining, diverting, sparkling, scintillating, silly, farcical, slapstick, side-splitting, rib-tickling, laugh-a-minute, wacky, zany, off the wall, a scream, rich, priceless, difficult to explain and understand, strange

Oh, is that what that means.

insanely great, as a cow has never seen



especially due to the "dtack" feature used in the bus, which is Motorola m68k-like, even if used in a RISC-like design
the above represents all the macro-states in the fsm, omitting details, as it's just a proof of concept,
even if underlines that states are interruptible (a particular not should be specified and discussed for the I/O load/store stage,
something like the /BERR exception (bus error) in m68k

in the the first version of Arise v0 interrupts and exception are evaluated only before the "fetch stage"
so, evaluated in the next cpu cycle, while Arise v1 is able to evaluate immediately

Arise v2 is currently just a software emulator, there is no HDL code yet, and its design adds more features,
including 256 windows of 32 registers each

it means this processor is able to handle up to 255 tasks
(256 less one, WID=0 is used by interrupts and exceptions, WID stands for WindowID),
within 32Kbyte of BRAM (internal ram, used as "soft registers")

no doubt it's hipster (and more insane, but funnier) than SPARC

SPARC has fixed-size windows (8 in, 8 local, and 8 out), but some other archs have variable window size, like Am29000.
Also interesting is the Mill architecture, which uses an operand "belt" of most recent instruction results, and can select any 16 to drop into the callee, which is similar to an arbitrary register window.

Interesting 29K and Mill (by "Gandalf" professor, aka Ivan Godard )
I have to study their ISA as they are completely unknown to me

Arise V1 and V2 come with two operating modes: { kernel, user }

in user mode, each task owns its private 32 registers, { r0..r31 }
in kernel mode, the kernel own its private 32 registers, { r0..r31 }, but can also access everything

so, from the kernel mode point of view, all the task's registers are accessible through load/store
as they appear "memory mapped" within the the first 32Kbyte of ram { 0x0000..0x7ffff }

task000 { r0..r31 } <---- mapped at 0x0000 in kernel mode, reserved to kernel, more specifically for interrupts/exceptions
task001 { r0..r31 } <---- mapped at 0x0200 in kernel mode, the user task can access each of them as common registers
task002 { r0..r31 }
task003 { r0..r31 }
..
task255 { r0..r31 }

in user mode, if a task attempts to access the { 0x0000..0x7ffff } range, a trap will issued forcing the kernel mode
with the CAUSE register set with { privilege violation, task attempted to access the registers area }

the ISA in Arise doesn't limit, the upper limit (how many windows registers you can have) is under the the process of putting a decision or plan into effect, more specifically you can virtually implement more than 256 windows (it requires 32Kbyte of BRAM inside the FPGA, and the equivalent silicon in HDL), if you have the resources, in my case, my fpga is limited to 48Kbyte of usable BRAM, bigger fpga add more BRAM

255 usable tasks are more than what I need, and everything else will be implemented with an external NVRAM (2Mbyte), plus a DRAM (8Mbyte), so, about the first prototype (I will use the Papilio/Pro board, Xilinx Spartan6e + expansion), I am feeling fine



What do you think about this feature of Arise ?

Register windows? In the XXI century? After all we know about architecture? Why dear lord, Why?

For the same reason I'm scheming up a stack machine (yet to be fully implemented, but coming soon to an 8051 clone near you!) - because we can .

commodorejohn wrote: For the same reason I'm scheming up a stack machine

the ZPU is a stack machine, it was designed just a few years ago, and people seems to love it

R-ten-K wrote: Why dear lord, Why?

Don't you like Berkeley RISC legacy (SPARC) ?
Do you prefer the Stanford University solution (MIPS) ?