kramlq wrote:
I wholeheartedly disagree. MIPS was a great CPU to write kernel level code for - you could be executing C code from a 1:1 mapped virtual window within a few hundred lines of boot assembly code. Virtual memory and the TLB were quite straightforward, and the CP0 model of kernel support features was quite clean. The only thing I didn't like was that if you needed to write code across many vendors MIPS processors, there was little on chip support for explicit feature detection. The MIPS32/MIPS64 series addressed this main shortcoming.
I never worked on compilers, but did plenty of disassembly and debugging, and never thought code generated was too bad either. I studied many processor architectures over the years, and always though the "features" like visible register windows on SPARC (and Itanium to an extent) were overkill and had the potential to add inefficiency to critical paths.
I'll admit, I have a soft spot for Alpha's setup. I'd love for a modern Alpha-style (Shenwei, we want modern Alpha systems on Taobao, y'hear?) ISA, but honestly POWER has gotten mature enough that the little ASM I have to do is pretty easy. I'll agree, SPARC is pretty awful in terms of design, but at least Fujitsu has made it pretty performant!
The MIPS code I've dealt with is dirty, the register spill problem was worse than other RISCs, and at the end of the day, the ISA never lived up to its potential.
ARM64 is pretty good if we see high performance on the same pricepoint as Intel. I don't mind x64, tbh, but AMD's offerings suck ass, so Intel is the only player I can take seriously, and we know how monocultures are.