Its been obsolete since the 386 - its dedication to backwards compatibility has held innovation in the software side of things back, and it is still designed around the same architecture which points to days where memory was expensive, and having everything done on the CPU was ideal.
Like what features?
Look around today, its the only CISC architecture still actively developed, unless you somehow count Itanium, and that isn't nicknamed Itanic for anything other than its massive failure in the marketplace.
The various mainframe architectures will be surprised to hear this - as will the Renesas RX, the 8051, etc. Additionally, Itanium was (if anything) hyper-RISC - rigidly fixed-length, rigidly load-store, and in-order, with a lot of internal machine state exposed. The fact that you think it was CISC speaks volumes about your familiarity with the platform. And by the way, Itanium was outselling SPARC for quite a while. "Massive failure" indeed.
ARM, MIPS and other RISC architectures have long overtaken the mobile market, and even today, if you compare the same class of Intel CPU to ARM and MIPS equivalents, the x86 produces about the same amount of output within a margin of 5%, but it consumes 30-40% more power and costs significantly more.
ARM, MIPS, et al have absorbed their share of CISC-isms and are no longer RISC in the original sense of the word; for instance, both ARM and MIPS have variable-length extensions (Thumb/Thumb2 and MIPS16 respectively.) x86 being less efficient is essentially a myth at this point - see
for an example of in-depth analysis with a proper test bench.
Plus, x86-native architectures all seem to blow don't they?
And yet 2.8GHz, 15-core Xeon outperforms a 16-core 3.7GHz SPARC64 - quite likely at substantially lower power, given that SPARC64 chips have historically been hanging out up around 200W. Funny, that.
Now let's talk about obsolescence. Oracle SPARC has no SIMD past VIS (64-bit SIMD - MMX-class.) It has an encoding that limits it to 32 GPRs without extremely nasty tricks like those introduced by Fujitsu in HPC-ACE. It has register windows, which significantly increase the complexity of modern register rename in out-of-order designs. And you're calling
The moral of the story here is that ISA is basically irrelevant
it exposes interesting microarchitectural functionality - like explicit support for multithreading, speculation, or instruction parallelism. ISA is like what style of columns you put on the porch of your house - it may influence the way the house is built, but ultimately it's not what makes the house solid or not.
http://spec.org/cpu2006/results/res2014 ... 29190.html
http://spec.org/cpu2006/results/res2014 ... 28687.html
http://www.tpc.org/tpch/results/tpch_re ... =114041601
http://www.tpc.org/tpch/results/tpch_re ... =114020603