We're fine, but with grey beards, grown up kids and a bit more fat around the waist.
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PubkeyAcceptedKeyTypes=+ssh-dss
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PermitRootLogin yes
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2. The Irix 6.2 (and later) operating systems for r8000s will
automatically patch any running program to remove the prefetch
instructions. This will not affect the performance on an r8000 but
it will avoid the r8000 prefetch problem. In rare cases, the
kernel will not be able to avoid the problem and will request that
the user run the binary through r8kpp to execute the repair
permanently.
Irinikus wrote: The R8000 seems to be an interesting chip!
I would seriously like to have a system with one installed someday.
Irinikus wrote: If I manage get it, I will install it in an Indigo2 Impact machine, when I eventually acquire one.
Irinikus wrote: I suppose that I can install the motherboard and CPU my current Indigo2 then.
khalidschofield wrote: Anyway install CPAN worked. My SSL module won't build probably because SSL is broken on the box.
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> wget http://search.cpan.org/CPAN/authors/id/M/MI/MIKEM/Net-SSLeay-1.81.tar.gz
> gunzip -c Net-SSLeay-1.81.tar.gz | tar xvf -
> cd Net-SSLeay-1.81
> /usr/nekoware/bin/perl Makefile.PL INC="-I/usr/nekoware/include"
> gmake
jaggies wrote: I don't have any graphics at this point. The priority is IRIX, then networking. Once I have networking working, it should be fairly straight forward to do remote-display until I figure out the graphics hardware.
Because documentation on the graphics engine is sparse, I think direct hardware emulation will never happen in a meaningful way.
I found a bug in my DMA code over the weekend where, as you suggest, the registers need to be preserved across transfers. If you assume the hardware does the simplest thing (leaving the registers untouched), it's usually rightBut software needs to actively preserve them. In this case the current count needs to be preserved across invocations.
Looks like IRIX will set up the full DMA chain (say a 256kB block) and then do two 128kB transfers. Ordinarily, the hardware would just handle this since the wd33c93 would stop once each transfer is complete. Initiating a second transfer presumably lets the DMA continue. It's kind of hard to tell based on looking at my logs.
I haven't uploaded this to github yet because the code is in pretty rough shape. I'm patching a rather old version of QEMU (2014) and the code is quite messy at this stage. First step is to understand what's going on.
I found the NetBSD source quite handy for understanding the hardware. They seem to know at least a few of the hardware tricks.