I asked Ian Mapleson to part of his last R8000 Indigo2, and he was kind enough to accept.
Thanks a million, Ian!

Code: Select all
veronne 58# hinv -v
FPU: MIPS R8010 Floating Point Chip Revision: 0.1
CPU: MIPS R8000 Processor Chip Revision: 2.2
1 75 MHZ IP26 Processor
Main memory size: 640 Mbytes
Secondary unified instruction/data cache size: 2 Mbytes
Instruction cache size: 16 Kbytes
Data cache size: 16 Kbytes
Integral SCSI controller 0: Version WD33C93B, revision D
Disk drive: unit 1 on SCSI controller 0 (unit 1)
Integral SCSI controller 1: Version WD33C93B, revision D
On-board serial ports: 2
On-board bi-directional parallel port
Graphics board: GU1-Extreme
Integral Ethernet: ec0, version 1
Iris Audio Processor: version A2 revision 1.1.0
EISA bus: adapter 0
veronne 59# gfxinfo
Graphics board 0 is "GR2" graphics.
Managed (":0.0") 1280x1024
8 GEs, 2 REs, 24 bitplanes, 4 auxplanes, 4 cidplanes, Z-buffer
GR2 revision 6, VB2.0
HQ2.1 rev A, GE7 rev B, RE3.1 rev A, VC1 rev B, MC rev D
unknown, assuming 19" monitor





















among more than 150 machines : Apollo, Data General, Digital, HP, IBM, MIPS before SGI , Motorola, NeXT, SGI, Solbourne, Sun...