Now when I succeeded with this, I decided to enter this under a topic of its own. The beginning of this story can be found at
viewtopic.php?f=14&t=16725329
Today I hooked up the systems, my Onyx2 rack + Origin racks. I have gotten a bunch of directory ram from tesla, so everything was ready.
It is a mix of 8xR12000@300MHz and 32xR10000@250MHz and I used the Xpresslink cables to connect the two systems.
I organized all memory I had, equally over the nodeboards. This took more than one bank on each nodeboard, and I put a directory ram into the first slot.
Then this happened
'Treating all as standard'
. Unfortunatelly not totally unexpected, and it ended in
So after unscrewing 40 philips screws and 40 hex socket screws, organizing memory and screwing it back together, I had to do it all over again.
This time I only put memory in the first bank.
I really don't like those compression connectors, my fingers hurts from that small Allen key
The MMSC and the quite long list of cpus in the osview.
And of course the 'hinv'
The interesting part of the 'hinv -v' . The memory that turns into 'premium' when you add directory ram.
Theoretically I could get 10Gb with the number of directory rams I have, but I didn't want to mess around more than necessary with the memory.
I let the 128Mb sticks stay where they where.
If anyone is interested in the whole 'hinv -v' I can post it too. It is quite long.
Here is also the short version of 'gfxinfo'
Now I need some demos to push its limits . Or I could connect 8x 21inch SGI monitors to it, if I have enough cables and some sturdy shelves.
I have two movie clips showing my power meter flashing as it measures the powerconsumption. I won't run it for longer periods of time
Today I hooked up the systems, my Onyx2 rack + Origin racks. I have gotten a bunch of directory ram from tesla, so everything was ready.
It is a mix of 8xR12000@300MHz and 32xR10000@250MHz and I used the Xpresslink cables to connect the two systems.
I organized all memory I had, equally over the nodeboards. This took more than one bank on each nodeboard, and I put a directory ram into the first slot.
Then this happened
Code: Select all
IP27 PROM SGI Version 6.156 built 11:27:56 AM Nov 18, 2003
*** Mixed standard and premium memory:
*** Treating all as standard.
Testing/Initializing memory ............... DONE
Copying PROM code to memory ............... DONE
Discovering local IO ......................
Code: Select all
*** This configuration requires all nodes to have premium DIMMS.
*** /hw/module/1/slot/n1 not premium
etc...
Going to die...
This time I only put memory in the first bank.
I really don't like those compression connectors, my fingers hurts from that small Allen key
The MMSC and the quite long list of cpus in the osview.
And of course the 'hinv'
Code: Select all
Processor 0: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 1: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 2: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 3: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 4: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 5: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 6: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 7: 300 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 2.3
FPU: MIPS R12010 Floating Point Chip Revision: 2.3
Processor 8: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 9: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 10: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 11: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 12: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 13: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 14: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 15: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 16: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 17: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 18: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 19: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 20: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 21: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 22: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 23: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 24: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 25: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 26: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 27: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 28: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 29: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 30: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 31: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 32: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 33: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 34: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 35: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 36: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 37: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 38: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 39: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Main memory size: 7168 Mbytes
Instruction cache size: 32 Kbytes
Data cache size: 32 Kbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Integral SCSI controller 16: Version Fibre Channel AIC-1160, revision 2
Integral SCSI controller 18: Version QL1040B (rev. 2), single ended
Integral SCSI controller 24: Version QL1040B, single ended
Disk drive: unit 2 on SCSI controller 24
Disk drive: unit 4 on SCSI controller 24
CDROM: unit 6 on SCSI controller 24
Integral SCSI controller 12: Version QL1040B, single ended
CDROM: unit 6 on SCSI controller 12
Integral SCSI controller 10: Version QL1040B (rev. 2), single ended
CDROM: unit 6 on SCSI controller 10
Integral SCSI controller 0: Version QL1040B (rev. 2), single ended
Disk drive: unit 1 on SCSI controller 0
Disk drive: unit 2 on SCSI controller 0
Disk drive: unit 3 on SCSI controller 0
Disk drive: unit 4 on SCSI controller 0
CDROM: unit 6 on SCSI controller 0
Integral SCSI controller 14: Version QL1040B (rev. 2), single ended
CDROM: unit 6 on SCSI controller 14
Integral SCSI controller 1: Version QL1040B (rev. 2), single ended
Integral SCSI controller 25: Version QL1040B, single ended
Integral SCSI controller 13: Version QL1040B, single ended
Integral SCSI controller 11: Version QL1040B (rev. 2), single ended
Integral SCSI controller 15: Version QL1040B (rev. 2), single ended
Integral SCSI controller 19: Version QL1040B (rev. 2), differential
Integral SCSI controller 17: Version Fibre Channel AIC-1160, revision 2
Integral SCSI controller 22: Version Fibre Channel QL2200
Integral SCSI controller 20: Version QL1040B (rev. 2), differential
Integral SCSI controller 23: Version Fibre Channel QL2200A
Integral SCSI controller 21: Version QL1040B (rev. 2), differential
IOC3/IOC4 serial port: tty25
IOC3/IOC4 serial port: tty1
IOC3/IOC4 serial port: tty2
IOC3/IOC4 serial port: tty26
IOC3/IOC4 serial port: tty17
IOC3/IOC4 serial port: tty18
IOC3/IOC4 serial port: tty13
IOC3/IOC4 serial port: tty14
IOC3/IOC4 serial port: tty11
IOC3/IOC4 serial port: tty12
IOC3/IOC4 serial port: tty16
IOC3/IOC4 serial port: tty15
IOC3/IOC4 serial port: tty19
IOC3/IOC4 serial port: tty20
IOC3/IOC4 serial port: tty21
IOC3/IOC4 serial port: tty22
IOC3/IOC4 serial port: tty23
IOC3/IOC4 serial port: tty24
IOC3 parallel port: plp2
Graphics board: InfiniteReality2
Integral Fast Ethernet: ef0, version 1, module 7, slot io1, pci 2
Fast Ethernet: ef12, version 1, module 1, slot io1, pci 2
Fast Ethernet: ef6, version 1, module 3, slot io1, pci 2
Fast Ethernet: ef5, version 1, module 2, slot io1, pci 2
Fast Ethernet: ef7, version 1, module 4, slot io1, pci 2
Fast Ethernet: ef8, version 1, module 7, slot io3, pci 0
Fast Ethernet: ef9, version 1, module 7, slot io3, pci 1
Fast Ethernet: ef10, version 1, module 7, slot io3, pci 2
Fast Ethernet: ef11, version 1, module 7, slot io3, pci 3
Iris Audio Processor: version RAD revision 7.0, number 2
Origin FIBRE CHANNEL board, module 7 slot 4: Revision 4
Origin MSCSI board, module 7 slot 10: Revision 4
Origin BASEIO board, module 2 slot 1: Revision 4
Origin BASEIO board, module 7 slot 1: Revision 4
Origin BASEIO board, module 1 slot 1: Revision 3
Origin BASEIO board, module 3 slot 1: Revision 3
Origin BASEIO board, module 4 slot 1: Revision 3
Origin MENET board, module 7 slot 3: Revision 4
DIVO Video: controller 1 unit 0: Input, Output
IOC3/IOC4 external interrupts: 5
IOC3/IOC4 external interrupts: 1
IOC3/IOC4 external interrupts: 3
IOC3/IOC4 external interrupts: 2
IOC3/IOC4 external interrupts: 4
The interesting part of the 'hinv -v' . The memory that turns into 'premium' when you add directory ram.
Code: Select all
Memory at Module 1/Slot 1: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
Memory at Module 1/Slot 2: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 1/Slot 3: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 1/Slot 4: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 2/Slot 1: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
Memory at Module 2/Slot 2: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 2/Slot 3: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 2/Slot 4: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 3/Slot 1: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
Memory at Module 3/Slot 2: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 3/Slot 3: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 3/Slot 4: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 4/Slot 1: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
Memory at Module 4/Slot 2: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 4/Slot 3: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 4/Slot 4: 256 MB (enabled)
Bank 0 contains 256 MB (Premium) DIMMS (enabled)
Memory at Module 7/Slot 1: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
Memory at Module 7/Slot 2: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
Memory at Module 7/Slot 3: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
Memory at Module 7/Slot 4: 512 MB (enabled)
Bank 0 contains 512 MB (Premium) DIMMS (enabled)
I let the 128Mb sticks stay where they where.
If anyone is interested in the whole 'hinv -v' I can post it too. It is quite long.
Here is also the short version of 'gfxinfo'
Code: Select all
Graphics board 0 is "KONAL" graphics.
Managed (":0.0") 1600x1200
Display has 8 channels
4 GEs (of 4), occmask = 0x0f
4MB external BEF ram, 32bit path
4 RM7 boards (of 4) 1/1/1/1
Texture Memory: 64MB/64MB/64MB/64MB
Large pixel depth
32K cmap, 64K external gamma
(Could not contact X server; thus, no XSGIvc information available)
Now I need some demos to push its limits . Or I could connect 8x 21inch SGI monitors to it, if I have enough cables and some sturdy shelves.
I have two movie clips showing my power meter flashing as it measures the powerconsumption. I won't run it for longer periods of time