SGI: hinv

Challenge L, 6*R4x00, 1GB, HIPPI

jan-jaap
Donor
From Wijchen, The Netherlands
Who joined June 17, 2004, 11:35 a.m.

Wrote the following at Feb. 2, 2010, 2:59 p.m...

Picked up last weekend:


IRIS 1# hinv


Processor 0: 250 MHZ IP19


CPU: MIPS R4400 Processor Chip Revision: 6.0


FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0


Processor 1: 250 MHZ IP19


CPU: MIPS R4400 Processor Chip Revision: 6.0


FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0


Processor 2: 250 MHZ IP19


CPU: MIPS R4400 Processor Chip Revision: 6.0


FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0


Processor 3: 250 MHZ IP19


CPU: MIPS R4400 Processor Chip Revision: 6.0


FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0


Processor 4: 100 MHZ IP19


CPU: MIPS R4400 Processor Chip Revision: 4.0


FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0


Processor 5: 100 MHZ IP19


CPU: MIPS R4400 Processor Chip Revision: 4.0


FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0


Secondary unified instruction/data cache size: 4 Mbytes


Secondary unified instruction/data cache size: 4 Mbytes


Secondary unified instruction/data cache size: 4 Mbytes


Secondary unified instruction/data cache size: 4 Mbytes


Secondary unified instruction/data cache size: 1 Mbyte


Secondary unified instruction/data cache size: 1 Mbyte


Data cache size: 16 Kbytes


Instruction cache size: 16 Kbytes


Main memory size: 1024 Mbytes, 2-way interleaved


I/O board, Ebus slot 5: IO4 revision 1


Integral EPC serial ports: 4


Integral Ethernet controller: et0, Ebus slot 5


EPC external interrupts


Integral SCSI controller 4: Version WD33C95A, differential, revision 1


Integral SCSI controller 3: Version WD33C95A, differential, revision 1


Integral SCSI controller 2: Version WD33C95A, differential, revision 1


Integral SCSI controller 1: Version WD33C95A, differential, revision 0


Disk drive: unit 1 on SCSI controller 1


Integral SCSI controller 0: Version WD33C95A, single ended, revision 0


CDROM: unit 4 on SCSI controller 0


HIPPI adapter: hippi0, slot 5 adap 6, firmware version 27161144


Integral EPC parallel port: Ebus slot 5


VME bus: adapter 0 mapped to adapter 21


VME bus: adapter 21


IRIS 2#

I picked up a Challenge DM as well. When I'm done with this box it will have 12*R10000 w. 2MB L2 and 2GB RAM. So this is a work in progress. I rearranged the RAM a bit to improve interleaving, and to get some confidence wanted to run the diagnostics. I get:

Code: Select all


IRIS login: diag


Password:


IRIX Release 6.2 IP19 IRIS


Copyright 1987-1996 Silicon Graphics, Inc. All Rights Reserved.


Last login: Tue Feb  2 13:28:21 PST 2010 on ttyd1


TERM = (vt100)


CPU: MIPS R4400 Processor Chip Revision: 4.0


CPU: MIPS R4400 Processor Chip Revision: 4.0


*********************************************************************


*** DETECTED DOWNLEVEL 100 Mhz R4400 PROCESSOR CHIP REVISION: 4.0 ***


***  ON THIS SYSTEM WHICH NEED TO BE UPDATED.                     ***


*** PLEASE LOGIN AS ROOT AND EXECUTE HINV TO SEE WHICH PROCESSORS ***


***  ARE DOWNLEVEL AND UPDATE THOSE PROCESSORS.                   ***


*********************************************************************

There's a HIPPI board installed, I was wondering why it was in a 'wrong' slot (not VME) until I put it in the right slot -- and now the front doesn't close anymore

Now this is a deep dark secret, so everybody keep it quiet

It turns out that when reset, the WD33C93 defaults to a SCSI ID of 0, and it was simpler to leave it that way... -- Dave Olson, in comp.sys.sgi
Currently in commercial service:

(2x)

In the museum : almost every MIPS/IRIX system.
Wanted : GM1 board for Professional Series GT graphics (030-0076-003, 030-0076-004)

zackwatt
From Kentucky
Who joined March 1, 2009, 9:53 a.m.

Wrote the following at Feb. 2, 2010, 3:28 p.m...

Pics Please!

Octane2 2x600 V12 8GB - Octane2 600 V12 2GB - Octane 2x400 V10 2GB
Indigo² 195 Max Impact 386MB - Indigo² 250 Extreme 386MB
O2 350 CRM 256MB - O2+ 400 CRM 512MB

"I'm totally unappreciated in my time. You can run this whole park from this room, with minimal staff, for up to three days. You think that kind of automation is easy? Or cheap? You know anybody who can network eight Connection Machines and de-bug two million lines of code for what I bid this job? Because if you can, I'd love to see him try."

Indyboy
From Lost in EU
Who joined Nov. 21, 2006, 9:05 a.m.

Wrote the following at Feb. 3, 2010, 3:23 a.m...

Is it possible to use more than 4 cpus (1 nodeboard) in a Challenge DM? :shock:

josehill
Moderator
From New England, USA
Who joined June 6, 2005, 9:53 p.m.

Wrote the following at Feb. 3, 2010, 3:58 a.m...

Indyboy wrote: Is it possible to use more than 4 cpus (1 nodeboard) in a Challenge DM?

I think jan-jaap was talking about getting the Challenge L up to 12 cpus. A Challenge DM can only go up to four cpus.

jan-jaap
Donor
From Wijchen, The Netherlands
Who joined June 17, 2004, 11:35 a.m.

Wrote the following at Feb. 3, 2010, 4:15 a.m...

josehill wrote:

Indyboy wrote: Is it possible to use more than 4 cpus (1 nodeboard) in a Challenge DM?

I think jan-jaap was talking about getting the Challenge L up to 12 cpus. A Challenge DM can only go up to four cpus.

Indeed. My intention is to transform the 'L' into the ultimate build system for old IRIX versions: running IRIX 5.3 with 12 R4400's or IRIX 6.2 with 12 * R10K's (with 2MB L2!). I already had two quad R10K IP25's, one in my Onyx, one as a spare. Now, with the 'DM' I got number three. In the 'L' was a quad 250MHz IP19, and again I had one already plus a quad 200MHz.

I'm currently just taking inventory of what I picked up, what works and what not, board revisions etc. Tonight I'll pull the 'downrev' IP19 and run diagnostics on this system, them I'll move on to the DM.

I'm kind of curious where the built-in limitation (single CPU board) of the DM is hiding -- backplane? system controller?

I have no intention to keep both systems around. If someone wants the Challenge DM, I can probably create a working system from the dual CPU board. Otherwise I'll dismantle it and keep all the power bricks, system controller and boards as spares / donors.

Now this is a deep dark secret, so everybody keep it quiet

It turns out that when reset, the WD33C93 defaults to a SCSI ID of 0, and it was simpler to leave it that way... -- Dave Olson, in comp.sys.sgi
Currently in commercial service:

(2x)

In the museum : almost every MIPS/IRIX system.
Wanted : GM1 board for Professional Series GT graphics (030-0076-003, 030-0076-004)

jan-jaap
Donor
From Wijchen, The Netherlands
Who joined June 17, 2004, 11:35 a.m.

Wrote the following at Feb. 3, 2010, 12:01 p.m...

zackwatt wrote: Pics Please!

I took off the skins before transporting it, I will clean them before I put them back on. I just put the front door on so my 15 month old son doesn't hurt himself on the sheet metal. Not that he cares about it, there are no buttons to press or beeping noises :mrgreen:

Now this is a deep dark secret, so everybody keep it quiet

It turns out that when reset, the WD33C93 defaults to a SCSI ID of 0, and it was simpler to leave it that way... -- Dave Olson, in comp.sys.sgi
Currently in commercial service:

(2x)

In the museum : almost every MIPS/IRIX system.
Wanted : GM1 board for Professional Series GT graphics (030-0076-003, 030-0076-004)

Indyboy
From Lost in EU
Who joined Nov. 21, 2006, 9:05 a.m.

Wrote the following at Feb. 3, 2010, 2:14 p.m...

I've managed to understand jan-jaap's sentences right after sending the comment :oops:

and decided not to touch my comment in hope that some interesting info will pop up :mrgreen:

Sorry for the pollution

jan-jaap
Donor
From Wijchen, The Netherlands
Who joined June 17, 2004, 11:35 a.m.

Wrote the following at Feb. 4, 2010, 2:37 p.m...

The Challenge DM is also back! It has two IO4's; I had to swap them because the NVRAM on the primary has died and this freaks out the system.

Code: Select all


IRIS 1# hinv -v


CPU Board at Slot 2: (Enabled)


Processor 0 at Slot 2/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)


Processor 1 at Slot 2/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)


Processor 2 at Slot 2/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)


Processor 3 at Slot 2/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)


CPU: MIPS R10000 Processor Chip Revision: 2.6


FPU: MIPS R10010 Floating Point Chip Revision: 0.0


Secondary unified instruction/data cache size: 2 Mbytes


Data cache size: 32 Kbytes


Instruction cache size: 32 Kbytes


Main memory size: 1024 Mbytes, 4-way interleaved


MC3 Memory Board at Slot 1: 512 MB of memory (Enabled)


Bank A contains 16 MB SIMMS (Enabled)


Bank B contains 16 MB SIMMS (Enabled)


Bank C contains 16 MB SIMMS (Enabled)


Bank D contains 16 MB SIMMS (Enabled)


Bank E contains 16 MB SIMMS (Enabled)


Bank F contains 16 MB SIMMS (Enabled)


Bank G contains 16 MB SIMMS (Enabled)


Bank H contains 16 MB SIMMS (Enabled)


MC3 Memory Board at Slot 3: 512 MB of memory (Enabled)


Bank A contains 16 MB SIMMS (Enabled)


Bank B contains 16 MB SIMMS (Enabled)


Bank C contains 16 MB SIMMS (Enabled)


Bank D contains 16 MB SIMMS (Enabled)


Bank E contains 16 MB SIMMS (Enabled)


Bank F contains 16 MB SIMMS (Enabled)


Bank G contains 16 MB SIMMS (Enabled)


Bank H contains 16 MB SIMMS (Enabled)


I/O board, Ebus slot 4: IO4 revision 1


I/O board, Ebus slot 5: IO4 revision 1


Integral EPC serial ports: 4


Integral Ethernet controller: et0, Ebus slot 5


EPC external interrupts


Integral SCSI controller 41: Version WD33C95A, differential, revision 0


Integral SCSI controller 40: Version WD33C95A, differential, revision 0


Integral SCSI controller 1: Version WD33C95A, differential, revision 0


Disk drive: unit 1 on SCSI controller 1


Integral SCSI controller 0: Version WD33C95A, single ended, revision 0


CDROM: unit 4 on SCSI controller 0


Integral SCSI controller 44: Version SCIP/WD33C95A, differential


Integral SCSI controller 43: Version SCIP/WD33C95A, differential


Integral SCSI controller 42: Version SCIP/WD33C95A, differential


CC synchronization join counter


Integral EPC parallel port: Ebus slot 4


Integral EPC parallel port: Ebus slot 5


VME bus: adapter 0 mapped to adapter 21


VME bus: adapter 21


IRIS 2#

Next, I'm going to install a second IP25. This should fail on a genuine DM, but I cannot find any difference between the system controllers of the DM and the L The L booted fine with the system controller of the DM, with 8 CPUs installed ...

Now this is a deep dark secret, so everybody keep it quiet

It turns out that when reset, the WD33C93 defaults to a SCSI ID of 0, and it was simpler to leave it that way... -- Dave Olson, in comp.sys.sgi
Currently in commercial service:

(2x)

In the museum : almost every MIPS/IRIX system.
Wanted : GM1 board for Professional Series GT graphics (030-0076-003, 030-0076-004)

jan-jaap
Donor
From Wijchen, The Netherlands
Who joined June 17, 2004, 11:35 a.m.

Wrote the following at Feb. 5, 2010, 12:28 p.m...

Booted the 'DM' with a second IP25 this evening, and got:

Code: Select all


>> hinv -b




System Bus Information:


Slot 1: MC3 memory board with 512 megabytes of memory (Enabled)


Slot 2: IP25 processor board with 4 cpus (Enabled)


Slot 3: IP25 processor board with 0 cpus (Enabled)


Slot 4: IO4 I/O peripheral controller board (Enabled)


Slot 5: IO4 I/O peripheral controller board (Enabled)

The '0 cpus' raised my blood pressure for a moment (as did the B+++ text on the LCD), but it turns out both IP25's work fine as long as they are in slot 2.

Guess I have to look again at what limits the DM ... but I have many other things to do so this project will be suspended for a short while.

Oh, and I tried again with the system controller of the Challenge L -- same result. Will have to inspect the backplane ...

Now this is a deep dark secret, so everybody keep it quiet

It turns out that when reset, the WD33C93 defaults to a SCSI ID of 0, and it was simpler to leave it that way... -- Dave Olson, in comp.sys.sgi
Currently in commercial service:

(2x)

In the museum : almost every MIPS/IRIX system.
Wanted : GM1 board for Professional Series GT graphics (030-0076-003, 030-0076-004)

Indyboy
From Lost in EU
Who joined Nov. 21, 2006, 9:05 a.m.

Wrote the following at Feb. 6, 2010, 3:11 p.m...

Thanks for your time and devotion! I'm eagerly waiting for your next observations or solutions for this problem. It'd to be nice to build a 16 proc system :mrgreen:

jan-jaap
Donor
From Wijchen, The Netherlands
Who joined June 17, 2004, 11:35 a.m.

Wrote the following at Feb. 7, 2010, 11:59 a.m...

Indyboy wrote: Thanks for your time and devotion! I'm eagerly waiting for your next observations or solutions for this problem. It'd to be nice to build a 16 proc system

Not possible, at least not in a deskside. Only 5 E-bus slots, and you need at least one for memory, and one for I/O. So max is 3 CPU boards. I'll have to settle for 12 * R10K 8-)

But they will be the 2MB L2 model.

Now this is a deep dark secret, so everybody keep it quiet

It turns out that when reset, the WD33C93 defaults to a SCSI ID of 0, and it was simpler to leave it that way... -- Dave Olson, in comp.sys.sgi
Currently in commercial service:

(2x)

In the museum : almost every MIPS/IRIX system.
Wanted : GM1 board for Professional Series GT graphics (030-0076-003, 030-0076-004)

josehill
Moderator
From New England, USA
Who joined June 6, 2005, 9:53 p.m.

Wrote the following at Feb. 7, 2010, 2:40 p.m...

Yep, you need a Challenge XL refrigerator, um, rack, to go past 12 cpus.

lunatic
From Heidelberg, Germany
Who joined Jan. 21, 2005, 3:07 a.m.

Wrote the following at Feb. 8, 2010, 2:25 p.m...

rumors are, that there is a screw on the backplane present on the DM that disables all but one ebus slot for CPU boards...
That said, I do have a DM running with more than one CPU board. I just can't say why it works, because I got it in that configuration.

Don't suffer from insanity...
Enjoy every minute of it.

Indyboy
From Lost in EU
Who joined Nov. 21, 2006, 9:05 a.m.

Wrote the following at Feb. 9, 2010, 11:19 p.m...

jan-jaap wrote:

Indyboy wrote: Thanks for your time and devotion! I'm eagerly waiting for your next observations or solutions for this problem. It'd to be nice to build a 16 proc system

Not possible, at least not in a deskside. Only 5 E-bus slots, and you need at least one for memory, and one for I/O. So max is 3 CPU boards. I'll have to settle for 12 * R10K But they will be the 2MB L2 model.

OK, my bad, I've had 12 proc system on my mind

According to lunatic it's possible so I'm really excited how it could be done.

jan-jaap
Donor
From Wijchen, The Netherlands
Who joined June 17, 2004, 11:35 a.m.

Wrote the following at Feb. 10, 2010, 2:06 a.m...

Indyboy wrote: According to lunatic it's possible so I'm really excited how it could be done.

Me too. It's just a curiosity thing; I have both the L and the DM sitting here so this is the perfect occasion.

I could simply install the R10K boards in the Challenge L and call it quits but that wouldn't be satisfying. I need to know how things work and how to hack them

Now this is a deep dark secret, so everybody keep it quiet

It turns out that when reset, the WD33C93 defaults to a SCSI ID of 0, and it was simpler to leave it that way... -- Dave Olson, in comp.sys.sgi
Currently in commercial service:

(2x)

In the museum : almost every MIPS/IRIX system.
Wanted : GM1 board for Professional Series GT graphics (030-0076-003, 030-0076-004)