baby steps--- this is still a work in progress as the monitor isn't working quite right but I'll post what I have now and update later as things progress.
Code:
IRIS 3# hinv -vm
CPU Board at Slot 2: (Enabled)
Processor 0 at Slot 2/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
Processor 1 at Slot 2/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
Processor 2 at Slot 2/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
Processor 3 at Slot 2/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.5
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
Main memory size: 192 Mbytes, 1-way interleaved
MC3 Memory Board at Slot 1: 256 MB of memory (Enabled)
Bank A contains 16 MB SIMMS (Enabled)
Bank B contains 16 MB SIMMS (Enabled)
Bank C contains 16 MB SIMMS (Enabled)
Bank D contains 16 MB SIMMS (Disabled)
Instruction cache size: 32 Kbytes
Data cache size: 32 Kbytes
Secondary unified instruction/data cache size: 2 Mbytes
Integral SCSI controller 0: Version WD33C95A, single ended, revision 0
Disk drive: unit 1 on SCSI controller 0 (unit 1)
Tape drive: unit 2 on SCSI controller 0: 8mm(8500) cartridge
CDROM: unit 4 on SCSI controller 0
Tape drive: unit 5 on SCSI controller 0: DAT
Integral SCSI controller 1: Version WD33C95A, differential, revision 0
Integral EPC serial ports: 4
Integral EPC parallel port: Ebus slot 3
Graphics board: InfiniteReality
Integral Ethernet controller: et0, Ebus slot 3
I/O board, Ebus slot 3: IO4 revision 1
VME bus: adapter 13
VME bus: adapter 0 mapped to adapter 13
EPC external interrupts
CPU Board at Slot 2: (Enabled)
Processor 0 at Slot 2/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
Processor 1 at Slot 2/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
Processor 2 at Slot 2/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
Processor 3 at Slot 2/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.5
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
Main memory size: 192 Mbytes, 1-way interleaved
MC3 Memory Board at Slot 1: 256 MB of memory (Enabled)
Bank A contains 16 MB SIMMS (Enabled)
Bank B contains 16 MB SIMMS (Enabled)
Bank C contains 16 MB SIMMS (Enabled)
Bank D contains 16 MB SIMMS (Disabled)
Instruction cache size: 32 Kbytes
Data cache size: 32 Kbytes
Secondary unified instruction/data cache size: 2 Mbytes
Integral SCSI controller 0: Version WD33C95A, single ended, revision 0
Disk drive: unit 1 on SCSI controller 0 (unit 1)
Tape drive: unit 2 on SCSI controller 0: 8mm(8500) cartridge
CDROM: unit 4 on SCSI controller 0
Tape drive: unit 5 on SCSI controller 0: DAT
Integral SCSI controller 1: Version WD33C95A, differential, revision 0
Integral EPC serial ports: 4
Integral EPC parallel port: Ebus slot 3
Graphics board: InfiniteReality
Integral Ethernet controller: et0, Ebus slot 3
I/O board, Ebus slot 3: IO4 revision 1
VME bus: adapter 13
VME bus: adapter 0 mapped to adapter 13
EPC external interrupts
Code:
IRIS 7# /usr/gfx/gfxinfo
Graphics board 0 is "KONAS" graphics.
Managed (":0.0") 1280x1024
Display has 2 channels
4 GEs (of 4), occmask = 0x0f
4MB external BEF ram, 32bit path
1 RM6 board (of 1) 1/0/0/0
Texture Memory: 16MB/-/-/-
Medium pixel depth
32K cmap
Sirius video option detected
(Could not contact X server; thus, no XSGIvc information available)
Graphics board 0 is "KONAS" graphics.
Managed (":0.0") 1280x1024
Display has 2 channels
4 GEs (of 4), occmask = 0x0f
4MB external BEF ram, 32bit path
1 RM6 board (of 1) 1/0/0/0
Texture Memory: 16MB/-/-/-
Medium pixel depth
32K cmap
Sirius video option detected
(Could not contact X server; thus, no XSGIvc information available)
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(Aldebaran) (Maradona) [Mac Air] (Messi)