SGI: Hardware

Ok, yesterday i had that eureka moment, after taking some time to think about some other forum posts related to other stuff, that lead me in some other mind flow direction. I don't know if this is just right but i did some conceptual analysis that could proof to be one step closer to make GIO to PCI interface. And here is my concept i did roll out just philosophically:

Phobos G100 and Phobos G130 (also G160 for I2) have at their core in fact PCI nic ic's from Digital/Intel that interface to GIO with altera ASIC's that connect to GIO bus directly. The function of altera ASIC's is to modify GIO signals to PCI logic signals, so the GIO <--> PCI interface is in fact already in there on every G100 / G130 / G160 card.

The G100 has pure PCI nic from Digital, whereas the G130 has the Intel nic that is PCI/CardBus. Both PCI interfaces are revision 2.1 which is the older PCI specification but still usable.

As i have few spare G100 cards, i would take one, desolder the network nic from it, desolder all un-needed network peripherals on the nic front-end, pull out all the nic chip pins with flat cables to custom testing board on top of it, isolate the PCI signals, solder an PCI connector, ultimately stick in some low power PCI 2.1 card eg. lan card to start with, to see if i can reach it. The hardware identification for G cards is probably stored in the altera asic, so the hardware signature will stay like that for now.

Sure this would not be a real PCI bridge with all the bells and whistles, but 1 - 1 interface, so only 1 pci card possible, with custom driver jingling, but still for some experimenting maybe more than enough.

Those would be preliminary steps, what do you guys think about this ?

cybercow wrote: what do you guys think about this ?

interesting

here I have to play with PCI 5v @33Mhz on an Atlas board for job purposes, firmware fun, but I am planning to attach a pci-fpga board, and when I will be skilled enough It may be I will think about the Shoehorn in order to provide a few new peripherals to Octane

cybercow wrote: The hardware identification for G cards is probably stored in the altera asic, so the hardware signature will stay like that for now.

No, the hardware identification comes from PCI configuration space register access, and are likely those of the DEC chip itself and in no way emulated by the FPGA chip.

cybercow wrote: Those would be preliminary steps, what do you guys think about this ?

There's a risk that not all PCI address lines are wired, since the board was designed with the DEC chip in mind. So not all PCI devices would work.

Also, the FPGA chip might have some GIO addresses hardcoded, and would not allow more than one PCI BAR to be set (the BAR being probably initialized by the FPGA upon powerup).

Last but not least, the FPGA probably handles bus timing for DMA operations, and might not work correctly if DMA transfers from another PCI device are larger than a particular limit, or cross specific alignment boundaries.

ivelegacy wrote:

cybercow wrote: what do you guys think about this ?

interesting

here I have to play with PCI 5v @33Mhz on an Atlas board for job purposes, firmware fun, but I am planning to attach a pci-fpga board, and when I will be skilled enough It may be I will think about the Shoehorn in order to provide a few new peripherals to Octane

Well Ivelegacy, you're a pro , regarding electronics i'm just a hobbyist trying to have some fun

miod wrote: There's a risk that not all PCI address lines are wired, since the board was designed with the DEC chip in mind. So not all PCI devices would work.

Also, the FPGA chip might have some GIO addresses hardcoded, and would not allow more than one PCI BAR to be set (the BAR being probably initialized by the FPGA upon powerup).

Last but not least, the FPGA probably handles bus timing for DMA operations, and might not work correctly if DMA transfers from another PCI device are larger than a particular limit, or cross specific alignment boundaries.

Really appreciating your thoughts and infos. Will try to catch the problems along the way, hopefully to get some help from you experts here. All the worse that can come up is one burned Indy and a ruined G100

Ok, here is the pinout of the DEC nic found in a G100. I did a quick sketchup with colored legend. From the required group everything is there, besides i'm still not sure what to do with the interrupt (int_l) pin, the PCI interface should have INT#A, INT#B, INT#C, INT#D, though they resides on the optional group. Also there is missing LOCK# signal for locked transaction also from the optional group. Still to see if everything required is wired up on the pcb.

@cybercow
what @miod has pointed out is the reason why I was talking about fpga: custom bus needs custom design

p.s.
it's not SGI, but about having fun with HW (without the complexity of SGI), this seems a good wicked plan

cybercow wrote: i'm still not sure what to do with the interrupt (int_l) pin, the PCI interface should have INT#A, INT#B, INT#C, INT#D, though they resides on the optional group.

A given PCI device will only have one interrupt pin, unless it advertize itself as a multifunction device, in which case the subdevices are allowed to use different interrupt pins. Since the DEC chip is not a multifunction device, it makes perfect sense for it to only have one outgoing interrupt pin, which allows the FPGA to route it straight to the GIO interrupt line - it is very unlikely that the FPGA has support for the other interrupt pins.